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Disambiguation of "Fujiwara, Hideo"

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Test generation for scan design circuits with tri-state modules and bidirectional terminals.

, , , , and . DAC, page 71-78. ACM/IEEE, (1983)

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Esther Fujiwara

Hideo Baba

Hideo Ohashi

Hideo Andreas Baba

Hideo Ikezawa-Hanada

 

Other publications of authors with the same name

A Layout Adjustment Problem for Disjoint Rectangles Preserving Orthogonal Order., , , and . GD, volume 1547 of Lecture Notes in Computer Science, page 183-197. Springer, (1998)Constraining Transition Propagation for Low-Power Scan Testing Using a Two-Stage Scan Architecture., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 54-II (5): 450-454 (2007)Strongly Secure Scan Design Using Generalized Feed Forward Shift Registers., and . IEICE Trans. Inf. Syst., 98-D (10): 1852-1855 (2015)Differential Behavior Equivalent Classes of Shift Register Equivalents for Secure and Testable Scan Design., , and . IEICE Trans. Inf. Syst., 94-D (7): 1430-1439 (2011)Synthesis and Enumeration of Generalized Shift Registers for Strongly Secure SR-Equivalents., and . IEICE Trans. Inf. Syst., 100-D (9): 2232-2236 (2017)Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester., , , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (7): 790-800 (2007)A Latency Optimal Superstabilizing Mutual Exclusion Protocol in Unidirectional Rings., , , and . J. Parallel Distributed Comput., 62 (5): 865-884 (2002)Handling the pin overhead problem of DFTs for high-quality and at-speed tests., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (9): 1105-1113 (2002)SPIRIT: a highly robust combinational test generation algorithm., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (12): 1446-1458 (2002)A Test Generation Method Based on k-Cycle Testing for Finite State Machines., , and . IOLTS, page 232-235. IEEE, (2019)