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Disambiguation of "Hong, Hao-Chiao"

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A fast-locking all-digital phase locked loop in 90nm CMOS for Gigascale systems.

, and . ISCAS, page 1134-1137. IEEE, (2014)

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Chiao Yeh

Kwan-Hua Chiao

Hui-Fang Chiao

Yun-Chuang Chiao

Shih-Yang Chiao

 

Other publications of authors with the same name

Testing the Fleischer-Laker switched-capacitor biquad using the diagnosis-after-test procedure., , and . ISOCC, page 179-184. IEEE, (2012)A fast-locking all-digital phase locked loop in 90nm CMOS for Gigascale systems., and . ISCAS, page 1134-1137. IEEE, (2014)A Fully Integrated BIST \(\Delta \Sigma \) ADC Using the In-Phase and Quadrature Waves Fitting Procedure., and . IEEE Trans. Instrumentation and Measurement, 63 (12): 2750-2760 (2014)A Digital Background Calibration Scheme for Pipelined ADCs Using Multiple-Correlation Estimation., and . ISCAS, page 1-5. IEEE, (2018)Gm-C filter with automatic calibration scheme., , , , , and . DDECS, page 206-209. IEEE, (2016)Design of a Fault-Injectable Fleischer-Laker Switched-Capacitor Biquad for Verifying the Static Linear Behavior Fault Model., and . Asian Test Symposium, page 62-66. IEEE Computer Society, (2013)An Enhanced Boundary Scan Architecture for Inter-Die Interconnect Leakage Measurement in 2.5D and 3D Packages., , , and . ATS, page 5-10. IEEE Computer Society, (2017)A 17-nW, 0.5V, 500S/s, rail-to-rail SAR ADC with 8.1 effective number of bits., and . VLSI-DAT, page 1-4. IEEE, (2014)A 0.20-V to 0.25-V, Sub-nW, Rail-to-Rail, 10-bit SAR ADC for Self-Sustainable IoT Applications., and . ISCAS, page 1-4. IEEE, (2018)Design-for-digital-testability 30 MHz second-order Σ-Δ modulator.. CICC, page 211-214. IEEE, (2004)