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Disambiguation of "Chabini, Noureddine"

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An approach for reducing dynamic power consumption in synchronous sequential digital designs.

, and . ASP-DAC, page 198-204. IEEE Computer Society, (2004)

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Noureddine Doumi

Noureddine Jaballah

Noureddine Benkhadda

Noureddine Yahi

Adel Noureddine

 

Other publications of authors with the same name

Decimal floating-point multiplier with binary-decimal compression based fixed-point multiplier., , , and . CCECE, page 1-6. IEEE, (2017)FPGA-Based Digital FIR Filters With Small Coefficients and Large Data Input., and . CCWC, page 218-221. IEEE, (2023)FPGA-Based 8x8 Bits Signed Multipliers Using LUTs., and . CCECE, page 366-370. IEEE, (2023)An approach for computing the initial state for retimed synchronous sequential circuits., and . HLDVT, page 123-130. IEEE Computer Society, (2007)Two level decomposition based matrix multiplication for FPGAs., , and . ICECS, page 427-430. IEEE, (2009)Asymmetric large size multiplication using embedded blocks with efficient compression technique in FPGAs., , and . ICECS, page 137-140. IEEE, (2011)An improved BCD adder using 6-LUT FPGAs., , and . NEWCAS, page 13-16. IEEE, (2012)Efficient FPGA-Based Realization of Complex Squarer and Complex Conjugate using Embedded Multipliers., , , and . SoCC, page 21-24. IEEE, (2006)Asymmetric Large Size Signed Multipliers Using Embedded Blocks in FPGAs., , and . IPDPS Workshops, page 271-277. IEEE, (2011)An Algorithm for Gate Resizing to Reduce Power Dissipation in Combinational Digital Designs., , and . ICECOCS, page 1-3. IEEE, (2022)