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Disambiguation of "Valero, Mateo"

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Runtime-Guided Management of Scratchpad Memories in Multicore Architectures.

, , , , , , , and . PACT, page 379-391. IEEE Computer Society, (2015)

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Ana Maria Mateo Rosell

Carlos Mateo Balmelli

Mateo Hermel

Alejandro Valero

Silvia Valero

 

Other publications of authors with the same name

Automatic generation of loop scheduling for VLIW., , , and . PACT, page 306-309. IFIP Working Group on Algol / ACM, (1995)Increasing Memory Bandwidth with Wide Buses: Compiler, Hardware and Performance Trade-Offs., , , and . International Conference on Supercomputing, page 12-19. ACM, (1997)Runtime-assisted cache coherence deactivation in task parallel programs., , , , and . SC, page 35:1-35:12. IEEE / ACM, (2018)Picos: A hardware runtime architecture support for OmpSs., , , , and . Future Gener. Comput. Syst., (2015)Novel SRAM bias control circuits for a low power L1 data cache., , , , and . NORCHIP, page 1-6. IEEE, (2012)Thread Lock Section-Aware Scheduling on Asymmetric Single-ISA Multi-Core., , , , and . IEEE Comput. Archit. Lett., 14 (2): 160-163 (2015)Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures., , , and . Int. J. Parallel Program., 32 (6): 447-474 (2004)Hybrid Transactional Memory with Pessimistic Concurrency Control., , , , , , , and . Int. J. Parallel Program., 39 (3): 375-396 (2011)RMS-TM: a comprehensive benchmark suite for transactional memory systems (abstracts only)., , , , , and . SIGMETRICS Perform. Evaluation Rev., 39 (3): 19 (2011)Dynamic Cache Partitioning Based on the MLP of Cache Misses., , , and . Trans. High Perform. Embed. Archit. Compil., (2011)