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Variable bit truncation technique for approximate stochastic computing (ASC).

, , , , and . ISOCC, page 73-74. IEEE, (2017)

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Analysis and measurement of timing jitter induced by radiated EMI noise in automatic test equipment., , , , , , , and . IEEE Trans. Instrumentation and Measurement, 52 (6): 1749-1755 (2003)Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems., , and . IEEE Trans. Instrumentation and Measurement, 59 (5): 1127-1133 (2010)A CMOS Low Power Fully Digital Adaptive Power Delivery System Based on Finite State Machine Control., , and . ISCAS, page 1149-1152. IEEE, (2007)Low power real time electronic neuron VLSI design using subthreshold technique., , , , , , , and . ISCAS (4), page 744-747. IEEE, (2004)Parallel decoding for multi-stage BCH decoder., , , , and . ISOCC, page 107-108. IEEE, (2016)Integrated circuits design using carbon nanotube field effect transistor.. ISOCC, page 125-126. IEEE, (2016)Approximate stochastic computing (ASC) for image processing applications., , , , and . ISOCC, page 31-32. IEEE, (2016)A design and integration of Parametric Measurement Unit on to a 600MHz DCL., , , and . ISOCC, page 435-438. IEEE, (2012)Performance assessment of analog circuits with carbon nanotube FET (CNFET)., , and . ACM Great Lakes Symposium on VLSI, page 163-166. ACM, (2010)Low-power side-channel attack-resistant asynchronous S-box design for AES cryptosystems., , and . ACM Great Lakes Symposium on VLSI, page 459-464. ACM, (2010)