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Single-level integrity and confidentiality protection for distributed shared memory multiprocessors., , , , and . HPCA, page 161-172. IEEE Computer Society, (2008)Streamlining Integrity Tree Updates for Secure Persistent Non-Volatile Memory., , , and . CoRR, (2020)MILR: Mathematically Induced Layer Recovery for Plaintext Space Error Correction of CNNs., , and . CoRR, (2020)Making secure processors OS- and performance-friendly., , , and . ACM Trans. Archit. Code Optim., 5 (4): 16:1-16:35 (2009)Write-Aware Management of NVM-based Memory Extensions., , and . ICS, page 9:1-9:12. ACM, (2016)SecureME: a hardware-software approach to full system security., , , and . ICS, page 108-119. ACM, (2011)Correlation Prefetching with a User-Level Memory Thread., , and . IEEE Trans. Parallel Distributed Syst., 14 (6): 563-580 (2003)Analyzing Secure Memory Architecture for GPUs., , , and . ISPASS, page 59-69. IEEE, (2021)Studying the impact of hardware prefetching and bandwidth partitioning in chip-multiprocessors., and . SIGMETRICS, page 37-48. ACM, (2011)Improving Cost, Performance, and Security of Memory Encryption and Authentication., , , , and . ISCA, page 179-190. IEEE Computer Society, (2006)