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Disambiguation of "Lee, Chen-Yi"

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A 0.5 V 4.85 Mbps Dual-Mode Baseband Transceiver With Extended Frequency Calibration for Biotelemetry Applications.

, , , and . IEEE J. Solid State Circuits, 44 (11): 2966-2976 (2009)

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Yi-Chen Chen

Yi Chen

Yi Chen

Yi-chun Chen

Jia-yi Chen

 

Other publications of authors with the same name

A low power turbo/Viterbi decoder for 3GPP2 applications., , , and . IEEE Trans. Very Large Scale Integr. Syst., 14 (4): 426-430 (2006)Efficient VLSI Architectures for a High-Performance Digital Image Communication System., , and . IEEE J. Sel. Areas Commun., 8 (8): 1481-1491 (1990)An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications., , and . IEEE Trans. Circuits Syst. II Express Briefs, 54-II (11): 954-958 (2007)A Robust Frequency Tracking Loop for Energy-Efficient Crystalless WBAN Systems., , and . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (10): 637-641 (2011)A Universal VLSI Architecture for Reed-Solomon Error-and-Erasure Decoders., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (9): 1960-1967 (2009)A 125 µW, Fully Scalable MPEG-2 and H.264/AVC Video Decoder for Mobile Applications., , , , , , and . IEEE J. Solid State Circuits, 42 (1): 161-169 (2007)A 26.9 K 314.5 Mb/s Soft (32400, 32208) BCH Decoder Chip for DVB-S2 System., , , and . IEEE J. Solid State Circuits, 45 (11): 2330-2340 (2010)An all-digital phase-locked loop (ADPLL)-based clock recovery circuit., , and . IEEE J. Solid State Circuits, 34 (8): 1063-1073 (1999)A new DLL-based approach for all-digital multiphase clock generation., and . IEEE J. Solid State Circuits, 39 (3): 469-475 (2004)An all-digital phase-frequency tunable clock generator for wireless OFDM communications systems., , , , and . SoCC, page 305-308. IEEE, (2007)