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A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures.

, , and . SAMOS, volume 4017 of Lecture Notes in Computer Science, page 373-384. Springer, (2006)

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Modelling and Evaluation of a Network on Chip Architecture Using SDL., , and . SDL Forum, volume 2708 of Lecture Notes in Computer Science, page 166-182. Springer, (2003)A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures., , and . SAMOS, volume 4017 of Lecture Notes in Computer Science, page 373-384. Springer, (2006)Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms., , , , , and . NOCS, page 97-106. IEEE Computer Society, (2008)An Efficient Router Architecture and Its FPGA Prototyping to Support Junction Based Routing in NoC Platforms., , and . DSD, page 297-300. IEEE Computer Society, (2013)Junction based routing: a scalable technique to support source routing in large NoC platforms., , and . NoCArc@MICRO, page 45-50. ACM, (2012)A Multi-level Routing Scheme and Router Architecture to Support Hierarchical Routing in Large Network on Chip Platforms., , and . Euro-Par Workshops, volume 6586 of Lecture Notes in Computer Science, page 153-161. Springer, (2010)An Abstraction to Support Design of Deadlock-free Routing Algorithms for Large and Hierarchical NoCs., and . CIT, page 59-66. IEEE Computer Society, (2011)A methodology for design of application specific deadlock-free routing algorithms for NoC systems., , , and . CODES+ISSS, page 142-147. ACM, (2006)HiRA: A methodology for deadlock free routing in hierarchical networks on chip., , , and . NOCS, page 2-11. IEEE Computer Society, (2009)Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions., , and . DSD, page 696-703. IEEE Computer Society, (2006)