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0.37mW/Gb/s low power SLVS transmitter for battery powered applications.

, , , , , , and . ISCAS, page 1955-1958. IEEE, (2012)

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A low-power two-line inversion method for driving LCD panels., , , , and . ISCAS, page 1995-1998. IEEE, (2012)Full chip integration of 3-d cross-point ReRAM with leakage-compensating write driver and disturbance-aware sense amplifier., , , , , , , , , and 2 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)A digital DLL with 4-cycle lock time and 1/4 NAND-delay accuracy., , , and . A-SSCC, page 1-4. IEEE, (2015)A tracked oversampling digital data recovery for Low Latency, fast acquisition, and high jitter tolerance., , , , , and . MWSCAS, page 1027-1030. IEEE, (2013)Architecture-Accuracy Co-optimization of ReRAM-based Low-cost Neural Network Processor., , , , , , and . ACM Great Lakes Symposium on VLSI, page 427-432. ACM, (2020)Binary/Ternary Vector Matrix Multiplier with 3T-2R CBRAM Cell., and . ISOCC, page 73-74. IEEE, (2021)Low Power 3T-2R Non-Volatile TCAM Cell with Dual Match-line., and . ICEIC, page 1-2. IEEE, (2019)A 16x16 Programmable Anlaog Vector Matrix Multiplier using CMOS compatible Floating gate device., , , , , and . ICEIC, page 1-4. IEEE, (2019)An all-digital PLL with supply insensitive digitally controlled oscillator., , , and . IEICE Electron. Express, 10 (5): 20120902 (2013)A 12.5-Gb/s near-GND transceiver for wire-line UHD video interfaces., , , , , , , , , and . ISCAS, page 1488-1491. IEEE, (2014)