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Disambiguation of "Zhou, Dajiang"

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Moving Target Detection Method for Passive Radar Using LEO Communication Satellite Constellation.

, , , , , , and . IGARSS, page 8090-8093. IEEE, (2023)

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Zhou Zhou

Zhou Zhou

Zhou Zhao

Yayun Zhou

Yaming Zhou

 

Other publications of authors with the same name

Live demonstration: FPGA based 3840×2160 video decoding and displaying system., , and . APCCAS, page 169-170. IEEE, (2014)A Hardware-Efficient Dual-Standard VLSI Architecture for MC Interpolation in AVS and H.264., and . ISCAS, page 2910-2913. IEEE, (2007)VLSI Implementation of HEVC Motion Compensation With Distance Biased Direct Cache Mapping for 8K UHDTV Applications., , , , and . IEEE Trans. Circuits Syst. Video Techn., 27 (2): 380-393 (2017)A Variable-Clock-Cycle-Path VLSI Design of Binary Arithmetic Decoder for H.265/HEVC., , , , and . IEEE Trans. Circuits Syst. Video Techn., 28 (2): 556-560 (2018)VLSI architecture of HEVC intra prediction for 8K UHDTV applications., , , and . ICIP, page 1273-1277. IEEE, (2014)Low-Complexity Rate-Distortion Optimization Algorithms for HEVC Intra Prediction., , , and . MMM (1), volume 8325 of Lecture Notes in Computer Science, page 541-552. Springer, (2014)Chain-NN: An energy-efficient 1D chain architecture for accelerating deep convolutional neural networks., , , and . DATE, page 1032-1037. IEEE, (2017)Framework and VLSI Architecture of Measurement-Domain Intra Prediction for Compressively Sensed Visual Contents., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 100-A (12): 2869-2877 (2017)A Low-Cost VLSI Architecture of Multiple-Size IDCT for H.265/HEVC., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 97-A (12): 2467-2476 (2014)Distortion Control and Optimization for Lossy Embedded Compression in Video Codec System., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 100-A (11): 2416-2424 (2017)