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ESRU: Extremely Low-Bit and Hardware-Efficient Stochastic Rounding Unit Design for Low-Bit DNN Training.

S. Chang, G. Yuan, A. Lu, M. Sun, Y. Li, X. Ma, Z. Li, Y. Xie, M. Qin, X. Lin, Z. Fang, and Y. Wang. DATE, page 1-6. IEEE, (2023)

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Klaus Geng

Hui Geng

Hong Geng

Xiaoyun Geng

Geng Lai

Other publications of authors with the same name

An Efficient End-to-End Deep Learning Training Framework via Fine-Grained Pattern-Based Pruning.C. Zhang, G. Yuan, W. Niu, J. Tian, S. Jin, D. Zhuang, Z. Jiang, Y. Wang, B. Ren, S. Song and 1 other author(s). CoRR, (2020)A Life-Cycle Energy and Inventory Analysis of Adiabatic Quantum-Flux-Parametron Circuits.M. Zabihi, Y. Xie, Z. Li, P. Dong, G. Yuan, O. Chen, M. Pedram, and Y. Wang. CoRR, (2023)A SOT-MRAM-based Processing-In-Memory Engine for Highly Compressed DNN Implementation.G. Yuan, X. Ma, S. Lin, Z. Li, and C. Ding. CoRR, (2019)Achieving Real-Time Execution of Transformer-based Large-scale Models on Mobile with Compiler-aware Neural Architecture Optimization.W. Niu, Z. Kong, G. Yuan, W. Jiang, J. Guan, C. Ding, P. Zhao, S. Liu, B. Ren, and Y. Wang. CoRR, (2020)NPAS: A Compiler-Aware Framework of Unified Network Pruning and Architecture Search for Beyond Real-Time Mobile Acceleration.Z. Li, G. Yuan, W. Niu, P. Zhao, Y. Li, Y. Cai, X. Shen, Z. Zhan, Z. Kong, Q. Jin and 6 other author(s). CVPR, page 14255-14266. Computer Vision Foundation / IEEE, (2021)Pruning-as-Search: Efficient Neural Architecture Search via Channel Pruning and Structural Reparameterization.Y. Li, P. Zhao, G. Yuan, X. Lin, Y. Wang, and X. Chen. IJCAI, page 3236-3242. ijcai.org, (2022)FORMS: Fine-grained Polarized ReRAM-based In-situ Computation for Mixed-signal DNN Accelerator.G. Yuan, P. Behnam, Z. Li, A. Shafiee, S. Lin, X. Ma, H. Liu, X. Qian, M. Bojnordi, Y. Wang and 1 other author(s). ISCA, page 265-278. IEEE, (2021)SupeRBNN: Randomized Binary Neural Network Using Adiabatic Superconductor Josephson Devices.Z. Li, G. Yuan, T. Yamauchi, M. Zabihi, Y. Xie, P. Dong, X. Tang, N. Yoshikawa, D. Tiwari, Y. Wang and 1 other author(s). MICRO, page 584-598. ACM, (2023)ESRU: Extremely Low-Bit and Hardware-Efficient Stochastic Rounding Unit Design for Low-Bit DNN Training.S. Chang, G. Yuan, A. Lu, M. Sun, Y. Li, X. Ma, Z. Li, Y. Xie, M. Qin, X. Lin and 2 other author(s). DATE, page 1-6. IEEE, (2023)Memristor crossbar-based ultra-efficient next-generation baseband processors.G. Yuan, C. Ding, R. Cai, X. Ma, Z. Zhao, A. Ren, B. Yuan, and Y. Wang. MWSCAS, page 1121-1124. IEEE, (2017)

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Disambiguation of "Yuan, Geng"

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ESRU: Extremely Low-Bit and Hardware-Efficient Stochastic Rounding Unit Design for Low-Bit DNN Training.

Please choose a person to relate this publication to

Klaus Geng

Hui Geng

Hong Geng

Xiaoyun Geng

Geng Lai

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Yuan, Geng"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML ESRU: Extremely Low-Bit and Hardware-Efficient Stochastic Rounding Unit Design for Low-Bit DNN Training.

Please choose a person to relate this publication to

Klaus Geng

Hui Geng

Hong Geng

Xiaoyun Geng

Geng Lai

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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ESRU: Extremely Low-Bit and Hardware-Efficient Stochastic Rounding Unit Design for Low-Bit DNN Training.