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Disambiguation of "Joshi, Rajiv V."

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"Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session).

, , , and . ISLPED, page 203-206. ACM, (2000)

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Rajiv Trehan

Rajiv Kumar

Paneerselvam Rajiv

Jidnyasa Joshi

Rajiv Shah

 

Other publications of authors with the same name

3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits., , and . IEEE Trans. Very Large Scale Integr. Syst., 21 (11): 2094-2105 (2013)Influence and model of gate oxide breakdown on CMOS inverters., , , , and . Microelectron. Reliab., 43 (9-11): 1439-1444 (2003)Overview of Circuits, Systems, and Applications of Spintronics., , , , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (3): 265-278 (2016)New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology., , , , and . ISLPED, page 168-171. ACM, (2003)Hierarchical Memory System With STT-MRAM and SRAM to Support Transfer and Real-Time Reinforcement Learning in Autonomous Drones., , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 9 (3): 485-497 (2019)SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes., , , , , , , and . ISLPED, page 87-92. ACM, (2008)Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory., , , , , , , , , and 47 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 27 (2): 253-280 (2019)The resilience wall: Cross-layer solution strategies., , , , , , , , , and 3 other author(s). VLSI-DAT, page 1-11. IEEE, (2014)Guest Editorial Emerging Memories - Technology, Architecture and Applications (Second Issue)., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (3): 261-264 (2016)A novel sample reuse methodology for fast statistical simulations with applications to manufacturing variability., and . ISQED, page 672-678. IEEE, (2012)