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Efficient Block Scheduling to Minimize Context Switching Time for Programmable Embedded Processors., , and . Des. Autom. Embed. Syst., 4 (4): 311-327 (1999)Improving the observability and controllability of datapaths foremulation-based debugging., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (11): 1529-1541 (1999)Enhanced FPGA reliability through efficient run-time fault reconfiguration., , and . IEEE Trans. Reliab., 49 (3): 296-304 (2000)Fault-Tolerant and Low-Power Sampling Schedules for Localized BASNs., and . IEEE J. Emerg. Sel. Topics Circuits Syst., 3 (1): 86-95 (2013)Optimal ILP-Based Approach for Throughput Optimization Using Simultaneous Algorithm/Architecture Matching and Retiming., , and . DAC, page 113-118. ACM Press, (1995)Engineering Change: Methodology and Applications to Behavioral and System Synthesis., and . DAC, page 604-609. ACM Press, (1999)Sequential Circuit Delay optimization Using Global Path Delays., , , and . DAC, page 483-489. ACM Press, (1993)Consistency-Based On-line Localization in Sensor Networks., , and . DCOSS, volume 4026 of Lecture Notes in Computer Science, page 529-545. Springer, (2006)Synthesis of DSP soft real-time multiprocessor systems-on-silicon., and . ICASSP, page 1901-1904. IEEE Computer Society, (1999)Heuristic techniques for synthesis of hard real-time DSP application specific systems., and . ICASSP, page 1240-1243. IEEE Computer Society, (1996)