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Disambiguation of "Nakano, Shinsuke"

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A 180-mW Linear MZM Driver in CMOS for Single-Carrier 400-Gb/s Coherent Optical Transmitter.

, , , , , , and . ECOC, page 1-3. IEEE, (2017)

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Tomoyo Nakano

Hiroshi Daniel Nakano

 

Other publications of authors with the same name

Ultra-Low Power Dissipation (<2.4 W) Coherent InP Modulator Module with CMOS Driver IC., , , , , , , , , and 1 other author(s). ECOC, page 1-3. IEEE, (2018)25-Gb/s clock and data recovery IC using latch-load combined with CML buffer circuit for delay generation with 65-nm CMOS., , , , , , , , , and 2 other author(s). ISCAS, page 1-4. IEEE, (2017)A 25-Gb/s 480-mW CMOS modulator driver using area-efficient 3D inductor peaking., , , , , and . A-SSCC, page 1-4. IEEE, (2015)A wideband current-reuse-RGC TIA circuit with low-power consumption., , , , , , and . IEICE Electron. Express, 16 (22): 20190615 (2019)A 137-mW, 4 ch × 25-Gbps Low-Power Compact Transmitter Flip-Chip-Bonded 1.3-μm LD-Array-on-Si., , , , , , , , , and 5 other author(s). OFC, page 1-3. IEEE, (2018)20.1-mW 8-Gbps UWB-IR millimeter-wave transmitter using an OOK pulse modulator based on CMOS inverters., , , , and . ISCAS, page 2696-2699. IEEE, (2014)A 180-mW Linear MZM Driver in CMOS for Single-Carrier 400-Gb/s Coherent Optical Transmitter., , , , , , and . ECOC, page 1-3. IEEE, (2017)A 25-Gb/s 13 mW clock and data recovery using C2MOS D-flip-flop in 65-nm CMOS., , , , , , , , and . VLSI-DAT, page 1-4. IEEE, (2018)