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Postroute gate sizing for crosstalk noise reduction., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (12): 1670-1677 (2004)Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis., , , , and . EDAC-ETC-EUROASIC, page 332-337. IEEE Computer Society, (1994)Improved sequential ATPG using functional observation information and new justification methods., , and . ED&TC, page 262-266. IEEE Computer Society, (1995)Efficient logic-level timing analysis using constraint-guided critical path search., and . IEEE Trans. Very Large Scale Integr. Syst., 4 (3): 346-355 (1996)Slope Propagation in Static Timing Analysis., , , , and . ICCAD, page 338-343. IEEE Computer Society, (2000)A Methodology for Chip-Level Electromigration Risk Assessment and Product Qualification., , , , , , and . ISQED, page 232-237. IEEE Computer Society, (2004)Static Electromigration Analysis for Signal Interconnects., , , , , and . ISQED, page 377-382. IEEE Computer Society, (2003)Integrated modelling of thermal and visual image generation., , and . CVPR, page 356-362. IEEE, (1989)Leakage Current Modeling in PD SOI Circuits., , and . ISQED, page 113-117. IEEE Computer Society, (2005)Post-Route Gate Sizing for Crosstalk Noise Reduction., , , , , , and . ISQED, page 171-176. IEEE Computer Society, (2003)