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A 265μW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS.

, , , , , , , , , , и . ISSCC, стр. 256-258. IEEE, (2019)

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Tsuneo Someya

Chika Inoue Someya

 

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