Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Logical effort model extension to propagation delay representation., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (9): 1677-1684 (2006)Temperature and voltage aware timing analysis: application to voltage drops., , , and . DATE, page 1012-1017. EDA Consortium, San Jose, CA, USA, (2007)Continuous representation of the performance of a CMOS library., , , , , and . ESSCIRC, page 595-598. IEEE, (2003)Temperature Dependency in UDSM Process., , , and . PATMOS, volume 3728 of Lecture Notes in Computer Science, page 693-703. Springer, (2005)Temperature Dependence in Low Power CMOS UDSM Process., , , , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 110-118. Springer, (2004)Timing analysis in presence of supply voltage and temperature variations., , , and . ISPD, page 10-16. ACM, (2006)Physical Extension of the Logical Effort Model., , , , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 838-848. Springer, (2004)Temperature- and Voltage-Aware Timing Analysis., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (4): 801-815 (2007)