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Disambiguation of "Bull, David M."

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A Low-Power 1-GHz Razor FIR Accelerator With Time-Borrow Tracking Pipeline and Approximate Error Correction in 65-nm CMOS.

, , and . IEEE J. Solid State Circuits, 49 (1): 84-94 (2014)

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David M Eche

David M Eche

David M Stec

David M Allen

Udalrich Büll

 

Other publications of authors with the same name

RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance., , , , , , , and . IEEE J. Solid State Circuits, 44 (1): 32-48 (2009)A power-efficient 32b ARM ISA processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation., , , , , and . ISSCC, page 284-285. IEEE, (2010)Circuit-Level Timing Error Tolerance for Low-Power DSP Filters and Transforms., , , and . IEEE Trans. Very Large Scale Integr. Syst., 21 (6): 989-999 (2013)A 0.6V all-digital body-coupled wakeup transceiver for IoT applications., , , , and . VLSIC, page 98-. IEEE, (2015)A low-power 1GHz razor FIR accelerator with time-borrow tracking pipeline and approximate error correction in 65nm CMOS., , and . ISSCC, page 428-429. IEEE, (2013)Analysis of adaptive clocking technique for resonant supply voltage noise mitigation., , and . ISLPED, page 128-133. IEEE, (2015)A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation., , , , , and . IEEE J. Solid State Circuits, 46 (1): 18-31 (2011)Correction to Ä Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation"., , , , , and . IEEE J. Solid State Circuits, 46 (3): 705 (2011)Power Integrity Analysis of a 28 nm Dual-Core ARM Cortex-A57 Cluster Using an All-Digital Power Delivery Monitor., , , and . IEEE J. Solid State Circuits, 52 (6): 1643-1654 (2017)GeST: An Automatic Framework For Generating CPU Stress-Tests., , , , and . ISPASS, page 1-10. IEEE, (2019)