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Disambiguation of "Ogata, Yuuki"

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32Gb/s 28nm CMOS time-interleaved transmitter compatible with NRZ receiver with DFE.

, , , , , , , , and . ISSCC, page 40-41. IEEE, (2013)

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Kikuaki Ogata

 

Other publications of authors with the same name

Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs., , , , and . IEEE J. Solid State Circuits, 53 (9): 2696-2708 (2018)A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution., , , , , , , , , and 6 other author(s). VLSIC, page 1-2. IEEE, (2014)A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS., , , , , , , , , and 10 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)A Single-Chip, 10-Gigabit Ethernet Switch LSI for Energy-Efficient Blade Servers., , , , , , , , , and 1 other author(s). GreenCom/CPSCom, page 404-411. IEEE Computer Society, (2010)Requirements for a Component Framework of Future Ubiquitous Computing., , , and . WSTFES, page 9-12. IEEE Computer Society, (2003)3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS., , , , , , , , , and 7 other author(s). ISSCC, page 64-65. IEEE, (2016)32Gb/s 28nm CMOS time-interleaved transmitter compatible with NRZ receiver with DFE., , , , , , , , and . ISSCC, page 40-41. IEEE, (2013)6.7 A 28Gb/s digital CDR with adaptive loop gain for optimum jitter tolerance., , , , and . ISSCC, page 122-123. IEEE, (2017)Energy Management of Smart Home by Model Predictive Control Based on EV State Prediction., and . ASCC, page 410-415. IEEE, (2019)Building Smart Appliance Integration Middleware on the OSGi Framework., , , and . ISORC, page 139-146. IEEE Computer Society, (2004)