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An Accurate Worst Case Timing Analysis for RISC Processors., , , , , , , , , и . IEEE Trans. Software Eng., 21 (7): 593-604 (1995)Copycat: A High Precision Real Time NAND Simulator., , , и . CoRR, (2016)A worst case timing analysis technique for instruction prefetch buffers., , и . Microprocess. Microprogramming, 40 (10-12): 681-684 (1994)Performance Evaluation of Dynamic Voltage Scaling Algorithms for Hard Real-Time Systems., , , , и . J. Low Power Electron., 1 (3): 207-216 (2005)Dynamic voltage scaling algorithm for fixed-priority real-time systems using work-demand analysis., , и . ISLPED, стр. 396-401. ACM, (2003)Analysis of Worst Case DMA Response Time in a Fixed-Priority Bus Arbitration Protocol., , , и . Real Time Syst., 23 (3): 209-238 (2002)Threaded Prefetching: A New Instruction Memory Hierarchy for Real-Time Systems., , , , и . Real Time Syst., 13 (1): 47-65 (1997)Cache-Conscious Limited Preemptive Scheduling., , , , и . Real Time Syst., 17 (2-3): 257-282 (1999)A Flexible Tradeoff Between Code Size and WCET Using a Dual Instruction Set Processor., , , и . SCOPES, том 3199 из Lecture Notes in Computer Science, стр. 244-258. Springer, (2004)FMMU: a hardware-accelerated flash map management unit for scalable performance of flash-based SSDs., , и . DAC, стр. 115:1-115:6. ACM, (2018)