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Disambiguation of "Hsu, Wei-Chou"

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Low power design of phase-change memory based on a comprehensive model.

, , , , , , , , , , , and . IET Comput. Digit. Tech., 4 (4): 285-292 (2010)

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Chou-hsü Huang

Kang Wei Chou

Wei Wen Hsu

Wei-Chu Hsü

Chi-wei Stephan Hsü

 

Other publications of authors with the same name

Normally-Off InAlN/GaN Fin-MOSHEMT with Fluorine Treatment., , and . DRC, page 1-2. IEEE, (2020)Low power design of phase-change memory based on a comprehensive model., , , , , , , , , and 2 other author(s). IET Comput. Digit. Tech., 4 (4): 285-292 (2010)Liquid Crystal Display (LCD) Supplied by Highly Integrated Dual-Side Dual-Output Switched-Capacitor DC-DC Converter With Only Two Flying Capacitors., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (2): 439-446 (2012)Assessment of structure variation in silicon nanowire FETs and impact on SRAM., , , and . Microelectron. J., 43 (5): 300-304 (2012)A dual-phase charge pump regulator with nano-ampere switched-capacitor CMOS voltage reference for achieving low output ripples., , and . ICECS, page 446-449. IEEE, (2008)MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization., , , , , , , , , and 3 other author(s). ESSDERC, page 9-12. IEEE, (2023)6-T SRAM performance assessment with stacked silicon nanowire MOSFETs., , , and . ISQED, page 610-614. IEEE, (2015)Investigations on In₀.₁₂Al₀.₈₈N/AlN/AlₓGa₁-ₓN/In₀.₁₂Al₀.₈₈N MOS-HFETs With Symmetrically-Graded Wide-Gap Channel and Drain Field-Plate Design., , , , and . IEEE Access, (2024)