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Disambiguation of "Sato, Toshinori"

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Topic 4: High-Performance Architecture and Compilers.

, , , and . Euro-Par, volume 7484 of Lecture Notes in Computer Science, page 204-205. Springer, (2012)

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Toshinori Kuwahara

Makoto Sato

Nobuko Sato

Fujio Sato

Satô Saburô

 

Other publications of authors with the same name

Exploiting Configurability for Correct Sign Calculation in an Approximate Adder., and . ISOCC, page 86-87. IEEE, (2018)Non-uniform Set-Associative Caches for Power-Aware Embedded Processors., and . EUC, volume 3207 of Lecture Notes in Computer Science, page 217-226. Springer, (2004)Topic 4: High-Performance Architecture and Compilers., , , and . Euro-Par, volume 7484 of Lecture Notes in Computer Science, page 204-205. Springer, (2012)Influence of Compiler Optimizations on Value Prediction., , , and . HPCN Europe, volume 2110 of Lecture Notes in Computer Science, page 312-321. Springer, (2001)A Selective Replacement Method for Timing-Error-Predicting flip-Flops., , , and . J. Circuits Syst. Comput., (2012)2.44-GFLOPS 300-MHz floating-point vector-processing unit for high-performance 3D graphics computing., , , , , , , , , and . IEEE J. Solid State Circuits, 35 (7): 1025-1033 (2000)Exploiting Configurable Approximations for Tolerating Aging-induced Timing Violations., and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 103-A (9): 1028-1036 (2020)The potential in energy efficiency of a speculative chip-multiprocessor., , and . SPAA, page 273-274. ACM, (2004)Realizing Energy-Efficient MultiCore Processors by Utilizing Speculative Thread-Level Parallelism., , , , , and . Int. J. Comput. Their Appl., 14 (2): 79-91 (2007)Improving timing error tolerance without impact on chip area and power consumption., , and . ISQED, page 373-378. IEEE, (2013)