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Disambiguation of "Narayanan, Pritish"

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Experimental prototyping of beyond-CMOS nanowire computing fabrics.

, , , , and . NANOARCH, page 134-139. IEEE Computer Society, (2013)

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Pritish Sinha

P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

 

Other publications of authors with the same name

Metal-Gated Junctionless Nanowire Transistors., , and . CoRR, (2014)Deep Learning with Limited Numerical Precision., , , and . ICML, volume 37 of JMLR Workshop and Conference Proceedings, page 1737-1746. JMLR.org, (2015)Programmable cellular architectures at the nanoscale., , and . Nano Commun. Networks, 1 (2): 77-85 (2010)AI hardware acceleration with analog memory: Microarchitectures for low energy at high speed., , , , , , , , , and . IBM J. Res. Dev., 63 (6): 8:1-8:14 (2019)Circuit Techniques for Efficient Acceleration of Deep Neural Network Inference with Analog-AI (Invited)., , , , , , , , , and 2 other author(s). ISCAS, page 1-5. IEEE, (2021)Analog-memory-based 14nm Hardware Accelerator for Dense Deep Neural Networks including Transformers., , , , , , , , , and 6 other author(s). ISCAS, page 3319-3323. IEEE, (2022)Impact of Phase-Change Memory Drift on Energy Efficiency and Accuracy of Analog Compute-in-Memory Deep Learning Inference (Invited)., , , , , , , , , and 11 other author(s). IRPS, page 1-10. IEEE, (2023)Nanowire field-programmable computing platform., , , , , , and . NANOARCH, page 23-25. IEEE Computer Society, (2013)Parameter variation sensing and estimation in nanoscale fabrics., , , , and . J. Parallel Distributed Comput., 74 (6): 2504-2511 (2014)A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh., , , , , , , , , and 5 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 31 (1): 114-127 (2023)