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Disambiguation of "Golz, John"

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A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier.

, , , , , , , , , , , , , , , , and . ISSCC, page 486-617. IEEE, (2007)

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Jochen Golz

Wilhelm Gölz

Immanuel Gölz

Karl Gölz

Hermann Gölz

 

Other publications of authors with the same name

A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS., , , , , , , , , and 11 other author(s). IEEE J. Solid State Circuits, 44 (4): 1216-1226 (2009)OfftargetFinder: a web tool for species-specific RNAi design., , , , , , and . Bioinform., 32 (8): 1232-1234 (2016)80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity., , , , , , , , , and 4 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)An 800-MHz embedded DRAM with a concurrent refresh mode., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 40 (6): 1377-1387 (2005)Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias., , , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (3): 373-384 (2016)A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 43 (1): 86-95 (2008)A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier., , , , , , , , , and 7 other author(s). ISSCC, page 486-617. IEEE, (2007)Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias., , , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (3): 373-384 (2016)80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 53 (3): 949-960 (2018)