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Scheduling an interval ordered precedence graph with communication delays and a limited number of processors.

, , , and . RAIRO Oper. Res., 47 (1): 73-87 (2013)

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Implementation of a Fast Fourier transform algorithm onto a manycore processor., , , and . DASIP, page 1-7. IEEE, (2015)Definition of the F-- Extension to Fortran 90., , , , , , and . LCPC, volume 1366 of Lecture Notes in Computer Science, page 292-306. Springer, (1997)In-Place Multicore SIMD Fast Fourier Transforms., , and . HPEC, page 1-6. IEEE, (2023)A clustered manycore processor architecture for embedded and accelerated applications., , , , , , , , , and 1 other author(s). HPEC, page 1-6. IEEE, (2013)An Introduction to Simplex Scheduling.. IFIP PACT, volume A-50 of IFIP Transactions, page 327-330. North-Holland, (1994)Novel Arithmetics in Deep Neural Networks Signal Processing for Autonomous Driving: Challenges and Opportunities., , , , and . IEEE Signal Process. Mag., 38 (1): 97-110 (2021)Co-Design and Abstraction of a Network-on-Chip Using Deterministic Network Calculus.. NOCS, page 25:1. IEEE, (2018)Distortion Approximation of a Compressed Softmax Layer., , , and . SSP, page 491-495. IEEE, (2021)Consolidating High-Integrity, High-Performance, and Cyber-Security Functions on a Manycore Processor.. DAC, page 154. ACM, (2019)Kalray MPPA®: Massively parallel processor array: Revisiting DSP acceleration with the Kalray MPPA Manycore processor.. Hot Chips Symposium, page 1-27. IEEE, (2015)