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Aligning single path loops to reduce the number of capacity cache misses., , and . SIGBED Review, 12 (1): 13-18 (2015)Grid Computing Implementation in Ad Hoc Networks., , , , and . SCSS (1), page 196-201. Springer, (2007)A Time-Predictable Instruction-Cache Architecture that Uses Prefetching and Cache Locking., , and . ISORC Workshops, page 74-79. IEEE Computer Society, (2015)A TDMA-Based arbitration scheme for mixed-criticality multicore platforms., , , , and . EBCCSP, page 1-6. IEEE, (2015)New algorithms for efficient scheduling in Grid Ad-Hoc networks., and . ITI, page 591-596. IEEE, (2009)Using a Local Prefetch Strategy to Obtain Temporal Time Predictability., and . ISORC Workshops, page 227-233. IEEE Computer Society, (2011)Towards a Time-Predictable Hierarchical Memory Architecture - Prefetching Options to be Explored., and . ISORC Workshops, page 219-225. IEEE Computer Society, (2010)Constructing Time-Predictable MPSoCs: Avoid Conflicts in Temporal Control., , and . MCSoC, page 321-328. IEEE Computer Society, (2016)Best Practice for Caching of Single-Path Code., , , and . WCET, volume 57 of OASIcs, page 2:1-2:12. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, (2017)Improving Performance of Single-Path Code through a Time-Predictable Memory Hierarchy., , , , and . ISORC, page 76-83. IEEE Computer Society, (2017)