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Lower VDD Operation of FPGA-Based Digital Circuits Through Delay Modeling and Time Borrowing.

J. Freijedo, M. Valdés, L. Costas, M. Moure, J. Rodríguez-Andina, J. Semião, F. Vargas, I. Teixeira, and J. Teixeira. J. Low Power Electron., 7 (2): 185-198 (2011)

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Jay Jorgenson

Konrad Jörgens

Helmut Jörgens

Ingeborg Jörges

Heinz Jörgens

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Process Variations-Aware Statistical Analysis Framework for Aging Sensors Insertion.J. Vázquez, V. Champac, J. Semião, I. Teixeira, M. Santos, and J. Teixeira. J. Electron. Test., 29 (3): 289-299 (2013)DRAM Performance Sensor.J. Semião, L. Santos, and M. Santos. HCI (7), volume 13308 of Lecture Notes in Computer Science, page 510-521. Springer, (2022)A Zeta-CSC Converter Combination for Single-Input and Bipolar Output.S. Litran, E. Durán, M. Ferrera, J. Semião, and R. Barroso. IECON, page 5721-5726. IEEE, (2019)Integration of a Real-Time Stochastic Routing Optimization Software with an Enterprise Resource Planner.P. Cardoso, G. Schütz, J. Semião, J. Monteiro, J. Rodrigues, A. Mazayev, E. Ey, and M. Viegas. GISTAM (Selected Papers), volume 582 of Communications in Computer and Information Science, page 124-141. Springer, (2015)From system level to defect-oriented test: a case study.O. Dias, J. Semião, M. Santos, I. Teixeira, and J. Teixeira. ETW, page 136-141. IEEE Computer Society, (1999)A distributed load scheduling mechanism for micro grids.J. Monteiro, J. Eduardo, P. Cardoso, and J. Semião. SmartGridComm, page 278-283. IEEE, (2014)Time Management for Low-Power Design of Digital Systems.J. Semião, J. Freijedo, J. Rodríguez-Andina, F. Vargas, M. Santos, I. Teixeira, and J. Teixeira. J. Low Power Electron., 4 (3): 410-419 (2008)Lower VDD Operation of FPGA-Based Digital Circuits Through Delay Modeling and Time Borrowing.J. Freijedo, M. Valdés, L. Costas, M. Moure, J. Rodríguez-Andina, J. Semião, F. Vargas, I. Teixeira, and J. Teixeira. J. Low Power Electron., 7 (2): 185-198 (2011)On-Line BIST for Performance Failure Prediction Under NBTI-Induced Aging in Safety-Critical Applications.R. Oliveira, J. Semião, I. Teixeira, M. Santos, and J. Teixeira. J. Low Power Electron., 7 (4): 562-572 (2011)Signal Integrity Enhancement in Digital Circuits.J. Semião, M. Rodríguez-Irago, J. Rodríguez-Andina, L. Piccoli, F. Vargas, M. Santos, I. Teixeira, and J. Teixeira. IEEE Des. Test Comput., 25 (5): 452-461 (2008)

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Disambiguation of "Semião, Jorge"

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Lower VDD Operation of FPGA-Based Digital Circuits Through Delay Modeling and Time Borrowing.

Please choose a person to relate this publication to

Jay Jorgenson

Konrad Jörgens

Helmut Jörgens

Ingeborg Jörges

Heinz Jörgens

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Semião, Jorge"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Lower VDD Operation of FPGA-Based Digital Circuits Through Delay Modeling and Time Borrowing.

Please choose a person to relate this publication to

Jay Jorgenson

Konrad Jörgens

Helmut Jörgens

Ingeborg Jörges

Heinz Jörgens

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
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Lower VDD Operation of FPGA-Based Digital Circuits Through Delay Modeling and Time Borrowing.