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Automatic extraction of micro-architectural models of communication fabrics from register transfer level designs.

, and . DATE, page 1413-1418. ACM, (2015)

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On Necessary and Sufficient Conditions for Deadlock-Free Routing in Wormhole Networks., and . IEEE Trans. Parallel Distributed Syst., 22 (12): 2022-2032 (2011)Towards the formal verification of cache coherency at the architectural level., and . ACM Trans. Design Autom. Electr. Syst., 17 (3): 20:1-20:16 (2012)A formalisation of XMAS, and . ACL2, volume 114 of EPTCS, page 111-126. (2013)Inference and Abstraction of the Biometric Passport., , and . ISoLA (1), volume 6415 of Lecture Notes in Computer Science, page 673-686. Springer, (2010)A Fast and Verified Algorithm for Proving Store-and-Forward Networks Deadlock-Free., and . PDP, page 3-10. IEEE Computer Society, (2011)A Formal Model of Lower System Layers.. FMCAD, page 191-192. IEEE Computer Society, (2006)A Decision Procedure for Deadlock-Free Routing in Wormhole Networks., and . IEEE Trans. Parallel Distributed Syst., 25 (8): 1935-1944 (2014)The axiomatization of override and update., , , and . J. Appl. Log., 8 (1): 141-150 (2010)Inference of channel types in micro-architectural models of on-chip communication networks., , and . VLSI-SoC, page 1-6. IEEE, (2014)Analysis of a Clock Synchronization Protocol for Wireless Sensor Networks., , and . FM, volume 5850 of Lecture Notes in Computer Science, page 516-531. Springer, (2009)