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A 28Gb/s transceiver with chirp-managed EDC for DML systems., , , , , , , , , and 1 other author(s). ISSCC, page 264-266. IEEE, (2018)A 100-GbE reverse gearbox IC in 40nm CMOS for supporting legacy 10- and 40-GbE standards., , , , , , , , and . VLSIC, page 212-. IEEE, (2015)An 86.71875GHz RF transceiver for 57.8125Gb/s waveguide links with a CDR-assisted carrier synchronization loop in 28nm., , , , , , , , , and 2 other author(s). ESSCIRC, page 181-184. IEEE, (2023)A 0.87 W Transceiver IC for 100 Gigabit Ethernet in 40 nm CMOS., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 50 (2): 399-413 (2015)A 25.78125Gbps Bi-directional Transceiver with Framed-Pulsewidth Modulation (FPWM) for Extended Reach Optical Links in 28nm CMOS., , , , , , , , , and 3 other author(s). VLSI Technology and Circuits, page 156-157. IEEE, (2022)A 50Gb/s PAM-4 Bi-Directional Plastic Waveguide Link with Carrier Synchronization Using PI-Based Costas Loop., , , , , , , , , and 6 other author(s). ISSCC, page 1-3. IEEE, (2022)An on-chip stochastic sigma-tracking eye-opening monitor for BER-optimal adaptive equalization., , , , and . CICC, page 1-4. IEEE, (2015)A 4×10-Gb/s Referenceless-and-Masterless Phase Rotator-Based Parallel Transceiver in 90-nm CMOS., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (6): 2310-2320 (2016)An Automatic Loop Gain Control Algorithm for Bang-Bang CDRs., , , , , , , , , and 1 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (12): 2817-2828 (2015)0.6-2.7-Gb/s Referenceless Parallel CDR With a Stochastic Dispersion-Tolerant Frequency Acquisition Technique., , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (6): 1219-1225 (2014)