( en | de | ru )

 

Disambiguation of "Xue, Chun Jason"

Author of the publication

copydeleteadd this publication to your clipboard
Reducing LDPC Soft Sensing Latency by Lightweight Data Refresh for Flash Read Performance Improvement.

, , , , , and . DAC, page 23:1-23:6. ACM, (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Xue Xue Zhang

Ian Jason

Cheng Xue

Jia Xue

Min Xue

 

Other publications of authors with the same name

Sleep-aware variable partitioning for energy-efficient hybrid PRAM and DRAM main memory., , , and . ISLPED, page 75-80. ACM, (2014)Software enabled wear-leveling for hybrid PCM main memory on embedded systems., , , , and . DATE, page 599-602. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Accurate personal ultraviolet dose estimation with multiple wearable sensors., , , , , , and . BSN, page 347-352. IEEE, (2016)WUCC: Joint WCET and Update Conscious Compilation for cyber-physical systems., , and . ASP-DAC, page 65-70. IEEE, (2013)Computation and data transfer co-scheduling for interconnection bus minimization., , , and . ASP-DAC, page 311-316. IEEE, (2009)Sleep-aware mode assignment in wireless embedded systems., , and . J. Parallel Distributed Comput., 71 (7): 1002-1010 (2011)I/O scheduling with mapping cache awareness for flash based storage systems., , , , and . EMSOFT, page 21:1-21:10. ACM, (2016)Boosting the Performance of SSDs via Fully Exploiting the Plane Level Parallelism., , , , , and . IEEE Trans. Parallel Distributed Syst., 31 (9): 2185-2200 (2020)Balanced loop retiming to effectively architect STT-RAM-based hybrid cache for VLIW processors., , , , , , and . SAC, page 1710-1716. ACM, (2016)Introduction to the Special Issue on NVM and Storage., and . ACM Trans. Storage, 14 (1): 2:1-2:2 (2018)