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Multi-hop routing of multi-terminal nets for evaluation of hybrid multi-FPGA boards.

, , и . FPT, стр. 298-301. IEEE, (2002)

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Sushil Chandra Roy

Pravin Chandra Jain

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Sushil Kumar

 

Другие публикации лиц с тем же именем

Efficient Embedding of Partitioned Circuits onto Multi-FPGA Boards., , и . FPL, том 1896 из Lecture Notes in Computer Science, стр. 201-210. Springer, (2000)Evaluation of Various Routing Architectures for Multi-FPGA Boards., , и . VLSI Design, стр. 262-267. IEEE Computer Society, (2000)Hybrid Multi-FPGA Board Evaluation by Limiting Multi-Hop Routing., , и . IEEE International Workshop on Rapid System Prototyping, стр. 66-. IEEE Computer Society, (2002)Hybrid Multi-FPGA Board Evaluation by Permitting Limited Multi-Hop Routing., , и . Des. Autom. Embed. Syst., 8 (4): 309-326 (2003)Multi-hop routing of multi-terminal nets for evaluation of hybrid multi-FPGA boards., , и . FPT, стр. 298-301. IEEE, (2002)