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Fixing the broken time machine: consistency-aware checkpointing for energy harvesting powered non-volatile processor., , , , , and . DAC, page 184:1-184:6. ACM, (2015)SLC-enabled Wear Leveling for MLC PCM Considering Process Variation., , , and . DAC, page 36:1-36:6. ACM, (2014)Shared Last-Level Cache Management and Memory Scheduling for GPGPUs with Hybrid Main Memory., , , , , and . ACM Trans. Embed. Comput. Syst., 17 (4): 77:1-77:25 (2018)Joint Profit and Process Variation Aware High Level Synthesis With Speed Binning., , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (9): 1640-1650 (2015)Dynamically Reconfigurable Architecture for High-Throughput Hash Function in Key-Value Store., , , and . HPCC/SmartCity/DSS, page 1964-1970. IEEE, (2019)Software assisted non-volatile register reduction for energy harvesting based cyber-physical system., , , , , and . DATE, page 567-572. ACM, (2015)Set variation-aware shared LLC management for CPU-GPU heterogeneous architecture., , , , , and . DATE, page 79-84. IEEE, (2018)Correlation-guided Placement for Nonvolatile FPGAs., , , , , , and . DAC, page 1-6. IEEE, (2023)Runtime and reconfiguration dual-aware placement for SRAM-NVM hybrid FPGAs., , , , , and . NVMSA, page 1-6. IEEE, (2017)Branch Prediction directed Dynamic instruction Cache Locking for embedded systems., , , and . RTCSA, page 209-216. IEEE Computer Society, (2013)