Author of the publication

An explicitly declared delayed-branch mechanism for a superscalar architecture.

, and . Microprocess. Microprogramming, 40 (10-12): 677-680 (1994)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

An explicitly declared delayed-branch mechanism for a superscalar architecture., and . Microprocess. Microprogramming, 40 (10-12): 677-680 (1994)Exploiting instruction-level parallelism in superscalar architecture.. University of Hertfordshire, UK, (1995)British Library, EThOS.Pentium MPP for OLTP applications., , , , , and . HICSS (1), page 95-102. IEEE Computer Society, (1995)Instruction Scheduling for a Superscalar Architecture., and . EUROMICRO, page 643-650. IEEE Computer Society, (1996)A superscalar architecture to exploit instruction level parallelism., , , , and . Microprocess. Microsystems, 20 (7): 391-400 (1997)OR Practice - The Army Manpower Long-Range Planning System., , , , and . Operations Research, 36 (1): 5-17 (1988)