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Disambiguation of "Bhattacharya, Bhargab B."

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A Parallel Algorithm to Compute the Shortest Paths and Diameter of a Graph and Its VLSI Implementation.

, , , and . IEEE Trans. Computers, 35 (11): 1000-1004 (1986)

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Subhamoy Bhattacharya

Chhaya Bhattacharya

Nupur Bhattacharya

Indrajit Bhattacharya

Asitesh Bhattacharya

 

Other publications of authors with the same name

On the Testable Design of Bilateral Bit-Level Systolic Arrays., and . ITC, page 1024-1033. IEEE Computer Society, (1991)Construction of isothetic covers of a digital object: A combinatorial approach., , and . J. Vis. Commun. Image Represent., 21 (4): 295-310 (2010)Euler vector for search and retrieval of gray-tone images., , , , and . IEEE Trans. Syst. Man Cybern. Part B, 35 (4): 801-812 (2005)On Finding Shortest Isothetic Path inside a Digital Object., , , and . IWCIA, volume 7655 of Lecture Notes in Computer Science, page 1-15. Springer, (2012)Finding the Orthogonal Hull of a Digital Object: A Combinatorial Approach., , , and . IWCIA, volume 4958 of Lecture Notes in Computer Science, page 124-135. Springer, (2008)COMEDI: Combinatorial Election of Diagnostic Vectors From Detection Test Sets for Logic Circuits., and . IEEE Trans. Very Large Scale Integr. Syst., 25 (4): 1467-1476 (2017)Via minimization in VLSI routing with movable terminals., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 8 (8): 917-920 (1989)Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability., , and . J. Electron. Test., 22 (2): 125-142 (2006)Test Generation for Flow-Based Microfluidic Biochips With General Architectures., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (10): 2530-2543 (2020)A Methodology for Testing Arbitrary Bilateral Bit-Level Systolic Arrays., , and . VLSI Design, 4 (3): 257-269 (1996)