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Disambiguation of "Lanuzza, Marco"

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Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines.

, , , and . Int. J. Circuit Theory Appl., 43 (11): 1523-1540 (2015)

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Hans-Ernst Marcolin

Monika Marcotty

Johannes Marcour

Carlos Javier Marcos Navas

Massimiliano Marcon

 

Other publications of authors with the same name

Device-to-System Level Simulation Framework for STT-DMTJ Based Cache Memory., , , and . ICECS, page 123-124. IEEE, (2019)An Energy Aware Variation-Tolerant Writing Termination Control for STT-based Non Volatile Flip-Flops., , , and . ICECS, page 158-161. IEEE, (2019)Low bit rate image compression core for onboard space applications., , , , and . IEEE Trans. Circuits Syst. Video Techn., 16 (1): 114-128 (2006)Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications., , and . ISLPED, page 161-166. ACM, (2005)FASTA: Revisiting Fully Associative Memories in Computer Microarchitecture., , , , and . IEEE Access, (2024)Smart Material Implication Using Spin-Transfer Torque Magnetic Tunnel Junctions for Logic-in-Memory Computing., , , , , and . CoRR, (2022)AIDA: Associative In-Memory Deep Learning Accelerator., , , and . IEEE Micro, 42 (6): 67-75 (2022)Trimming-Less Voltage Reference for Highly Uncertain Harvesting Down to 0.25 V, 5.4 pW., , , , , and . IEEE J. Solid State Circuits, 56 (10): 3134-3144 (2021)Efficient Implementation of Many-Ported Memories by Using Standard-Cell Memory Approach., , , , and . IEEE Access, (2023)Double-precision Dual Mode Logic carry-save multiplier., , and . Integr., (2019)