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Towards hybrid last level caches for chip-multiprocessors., , , and . SIGARCH Comput. Archit. News, 36 (2): 56-63 (2008)Towards modeling & analysis of consolidated CMP servers., , and . SIGARCH Comput. Archit. News, 36 (2): 38-45 (2008)Advances in Microprocessor Cache Architectures Over the Last 25 Years., , , , , , , , and . IEEE Micro, 41 (6): 78-88 (2021)Visual IoT: Architectural Challenges and Opportunities; Toward a Self-Learning and Energy-Neutral IoT., and . IEEE Micro, 36 (6): 45-49 (2016)VM3: Measuring, modeling and managing VM shared resources., , , , , and . Comput. Networks, 53 (17): 2873-2887 (2009)Characterization and Evaluation of Cache Hierarchies for Web Servers.. World Wide Web, 7 (3): 259-280 (2004)Low-Power, Resilient Interconnection with Orthogonal Latin Squares., , , , and . IEEE Des. Test Comput., 28 (2): 30-39 (2011)Performance of Multistage Bus Networks for a Distributed Shared Memory Multiprocessor., , , , and . IEEE Trans. Parallel Distributed Syst., 8 (1): 82-95 (1997)Trends and Opportunities for SRAM Based In-Memory and Near-Memory Computation., , , , , , , , , and . ISQED, page 547-552. IEEE, (2021)I/O processing in a virtualized platform: a simulation-driven approach., , , , , and . VEE, page 116-125. ACM, (2007)