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Towards a sub-2.5V, 100-Gb/s Serial Transceiver., , , , , , , , and . CICC, page 471-478. IEEE, (2007)A 35-GS/s, 4-Bit Flash ADC With Active Data and Clock Distribution Trees., , and . IEEE J. Solid State Circuits, 44 (6): 1709-1720 (2009)Design of a Dual W- and D-Band PLL., , , , , , and . IEEE J. Solid State Circuits, 46 (5): 1011-1022 (2011)A 13.2-dBm, 138-GHz I/Q RF-DAC with 64-QAM and OFDM free-space constellation formation., , , and . ESSCIRC, page 191-194. IEEE, (2017)A 45nm SOI CMOS Class-D mm-Wave PA with >10Vpp differential swing., , , , and . ISSCC, page 88-90. IEEE, (2012)A 2x-Oversampling, 128-GS/s 5-bit Flash ADC for 64-GBaud Applications., , and . BCICTS, page 52-55. IEEE, (2018)65-nm CMOS, W-Band Receivers for Imaging Applications., , , , and . CICC, page 749-752. IEEE, (2007)A High Modulation Bandwidth, 110 GHz Power-DAC Cell for IQ Transmitter Arrays With Direct Amplitude and Phase Modulation., , and . IEEE J. Solid State Circuits, 49 (10): 2103-2113 (2014)An inductor-based 52-GHz 0.18 μm SiGe HBT cascode LNA with 22 dB gain., and . ESSCIRC, page 287-290. IEEE, (2004)Large-Swing 22nm Si/SiGe FDSOI Stacked Cascodes for 56GBaud Drivers and 5G PAs., , and . BCICTS, page 267-270. IEEE, (2018)