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Low-power VLSI design for motion estimation using adaptive pixel truncation.

, , , and . IEEE Trans. Circuits Syst. Video Techn., 10 (5): 669-678 (2000)

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Design Trade-Offs for Real-Time Block Matching Motion Estimation Algorithms., and . ACCV, volume 1035 of Lecture Notes in Computer Science, page 129-138. Springer, (1995)Low-power VLSI design for motion estimation using adaptive pixel truncation., , , and . IEEE Trans. Circuits Syst. Video Techn., 10 (5): 669-678 (2000)Design of fast motion estimation algorithm based on hardware consideration., and . IEEE Trans. Circuits Syst. Video Techn., 7 (5): 819-823 (1997)Generic VLSI architecture for block-matching motion estimation algorithms., , , and . Int. J. Imaging Systems and Technology, 9 (4): 257-273 (1998)Cost Effective VLSI Architectures for Full-Search Block-Matching Motion Estimation Algorithm., and . VLSI Signal Processing, 17 (2-3): 225-240 (1997)Low power motion estimation design using adaptive pixel truncation., , , and . ISLPED, page 167-172. ACM, (1997)