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Disambiguation of "Carloni, Luca P."

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Silicon Photonics Codesign for Deep Learning.

, , , , , and . Proc. IEEE, 108 (8): 1261-1282 (2020)

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Olivier Carloni

Luca Rizzini

Luca Tranchini

Luca Tuninetti

Alfonz Luca

 

Other publications of authors with the same name

PR-ESP: An Open-Source Platform for Design and Programming of Partially Reconfigurable SoCs., , , , and . DATE, page 1-6. IEEE, (2023)A Scalable Black-Box Optimization System for Auto-Tuning VLSI Synthesis Programs., , , , , and . RES4ANT@DATE, volume 1643 of CEUR Workshop Proceedings, page 8-12. CEUR-WS.org, (2016)Rialto: a bridge between description and implementation of control algorithms for wireless sensor networks., , and . EMSOFT, page 183-186. ACM, (2005)Photonic Network-on-Chip Design., , , , and . Integrated Circuits and Systems Springer, (2014)KAIROS: Incremental Verification in High-Level Synthesis through Latency-Insensitive Design., , and . FMCAD, page 105-109. IEEE, (2019)Compiler-Assisted Selection of Hardware Acceleration Candidates from Application Source Code., , , , , and . ICCD, page 129-137. IEEE, (2019)High-level synthesis of accelerators in embedded scalable platforms., , and . ASP-DAC, page 204-211. IEEE, (2016)Panel: the heritage of Mead & Conway: what has remained the same, what was missed, what has changed, what lies ahead., , , , , , and . DATE, page 171-175. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Leveraging Prior Knowledge for Effective Design-Space Exploration in High-Level Synthesis., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (11): 3736-3747 (2020)Theory of latency-insensitive design., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (9): 1059-1076 (2001)