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A Novel Approach to Accurate Timing Verification Using RTL Descriptions.

, and . DAC, page 638-641. ACM Press, (1989)

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Design of Test Pattern Generators for Built-In Test., , and . ITC, page 315-319. IEEE Computer Society, (1984)Research in Reliable VLSI Architectures at the University of Illinois.. FJCC, page 890-893. IEEE Computer Society, (1986)Forward Recovery Using Checkpointing in Parallel Systems., , and . ICPP (1), page 272-275. Pennsylvania State University Press, (1990)An oscillation-based test structure for timing information extraction., , , and . VTS, page 74-79. IEEE Computer Society, (2012)Abstraction of data path registers for multilevel verification of large circuits., , , and . Great Lakes Symposium on VLSI, page 11-14. IEEE, (1994)Design and evaluation of fault tolerance techniques for highly parallel architectures.. Great Lakes Symposium on VLSI, IEEE, (1991)Quantitative evaluation of soft error injection techniques for robust system design., , , , and . DAC, page 101:1-101:10. ACM, (2013)Non-speculative double-sampling technique to increase energy-efficiency in a high-performance processor., , and . DATE, page 254-257. EDA Consortium San Jose, CA, USA / ACM DL, (2013)FERRARI: A Tool for The Validation of System Dependability Properties., , and . FTCS, page 336-344. IEEE Computer Society, (1992)Hierarchical design and analysis of fault-tolerant multiprocessor systems using concurrent error detection., and . FTCS, page 130-137. IEEE Computer Society, (1990)