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Synthesis of Nondeterministic Behavior in Recombinase-Based Genetic Circuits.

, , and . ISMVL, page 200-205. IEEE, (2019)

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When Boolean Satisfiability Meets Gaussian Elimination in a Simplex Way., and . CAV, volume 7358 of Lecture Notes in Computer Science, page 410-426. Springer, (2012)SPOCK: Static Performance Analysis and Deadlock Verification for Efficient Asynchronous Circuit Synthesis., , and . ICCAD, page 442-449. IEEE, (2015)Optimum loading dispersion for high-speed tree-type decision circuitry., and . ICCAD, page 520-525. IEEE Computer Society, (1999)Hardware Equivalence and Property Verification., , , and . Boolean Models and Methods, Cambridge University Press, (2010)Circuit Learning for Logic Regression on High Dimensional Boolean Space., , , and . DAC, page 1-6. IEEE, (2020)To SAT or Not to SAT: Scalable Exploration of Functional Dependency., , , and . IEEE Trans. Computers, 59 (4): 457-467 (2010)Retiming and Resynthesis: A Complexity Perspective., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (12): 2674-2686 (2006)On the verification of sequential equivalence., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (6): 686-697 (2003)Bi-decomposing large Boolean functions via interpolation and satisfiability solving., , and . DAC, page 636-641. ACM, (2008)Functional Dependency for Verification Reduction., and . CAV, volume 3114 of Lecture Notes in Computer Science, page 268-280. Springer, (2004)