( en | de | ru )

 

Disambiguation of "Jayakumar, Nikhil"

Author of the publication

copydeleteadd this publication to your clipboard
Practical techniques to reduce skew and its variations in buffered clock networks.

, , , , , , , and . ICCAD, page 592-596. IEEE Computer Society, (2005)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Nikhil Sasidharan

Tammana Jayakumar

Nikhil Ratanje

Nikhil Jethava

Nikhil Karamchandani

 

Other publications of authors with the same name

A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations., , , and . Integr., 41 (3): 399-412 (2008)A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations., , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (2): 269-277 (2009)High-throughput VLSI Implementations of Iterative Decoders and Related Code Construction Problems., , , , and . VLSI Signal Processing, 49 (1): 185-206 (2007)A design flow to optimize circuit delay by using standard cells and PLAs., , , , , and . ACM Great Lakes Symposium on VLSI, page 217-222. ACM, (2006)High-throughput VLSI implementations of iterative decoders and related code construction problems., , , and . GLOBECOM, page 361-365. IEEE, (2004)An algebraic decision diagram (ADD) based technique to find leakage histograms of combinational designs., , and . ISLPED, page 111-114. ACM, (2005)Dynamically De-Skewable Clock Distribution Methodology., , and . IEEE Trans. Very Large Scale Integr. Syst., 16 (9): 1220-1229 (2008)An Automated Approach for Minimum Jitter Buffered H-Tree Construction., , , , and . VLSI Design, page 76-81. IEEE Computer Society, (2011)A low-jitter phase-locked resonant clock generation and distribution scheme., , , , and . ICCD, page 487-490. IEEE Computer Society, (2013)A variation tolerant subthreshold design approach., and . DAC, page 716-719. ACM, (2005)