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Design Strategies for Optimal Multiplier Circuits.

, , , and . IEEE Symposium on Computer Arithmetic, page 42-49. IEEE Computer Society, (1995)

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Design strategies for optimal hybrid final adders in a parallel multiplier., and . VLSI Signal Processing, 14 (3): 321-331 (1996)Optimal Circuits for Parallel Multipliers., , , and . IEEE Trans. Computers, 47 (3): 273-285 (1998)Implementing Multiply-Accumulate Operation in Multiplication Time., and . IEEE Symposium on Computer Arithmetic, page 99-. IEEE Computer Society, (1997)Design Strategies for Optimal Multiplier Circuits., , , and . IEEE Symposium on Computer Arithmetic, page 42-49. IEEE Computer Society, (1995)