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An implementation of the SANE Virtual Processor using POSIX threads., , , and . J. Syst. Archit., 55 (3): 162-169 (2009)A general model of concurrency and its implementation as many-core dynamic RISC processors., , , , , , and . ICSAMOS, page 1-9. IEEE, (2008)Evaluating CMPs and Their Memory Architecture., , and . ARCS, volume 5455 of Lecture Notes in Computer Science, page 246-257. Springer, (2009)Apple-CORE: Harnessing general-purpose many-cores with hardware concurrency management., , , , , , and . Microprocess. Microsystems, 37 (8-C): 1090-1101 (2013)Implementation and evaluation of a microthread architecture., , , and . J. Syst. Archit., 55 (3): 149-161 (2009)MGSim - Simulation tools for multi-core processor architectures, , , , , and . CoRR, (2013)MGSim - A simulation environment for multi-core research and education., , , , , and . ICSAMOS, page 80-87. IEEE, (2013)Making multi-cores mainstream - from security to scalability., , , , and . PARCO, volume 19 of Advances in Parallel Computing, page 16-31. IOS Press, (2009)Heterogeneous integration to simplify many-core architecture simulations., , , , and . RAPIDO, page 17-24. ACM, (2012)Apple-CORE: Microgrids of SVP Cores - Flexible, General-Purpose, Fine-Grained Hardware Concurrency Management., , , , , and . DSD, page 501-508. IEEE Computer Society, (2012)