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Disambiguation of "Sin, Sai-Weng"

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A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation.

, , , , and . IEEE J. Solid State Circuits, 56 (8): 2375-2387 (2021)

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Sai Li

Sai Zhang

Sai Zhang

Sai Qian

Sin Wong

 

Other publications of authors with the same name

Quantitative noise analysis of jitter-induced nonuniformly sampled-and-held signals., , and . ICASSP (6), page 253-256. IEEE, (2003)A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC., , , , , and . IEEE J. Solid State Circuits, 48 (8): 1783-1794 (2013)A generalized timing-skew-free, multi-phase clock generation platform for parallel sampled-data systems., , and . ISCAS (1), page 369-372. IEEE, (2004)Timing-mismatch analysis in high-speed analog front-end with nonuniformly holding output., , , and . ISCAS (1), page 129-132. IEEE, (2003)Review and Selection Strategy for High-Accuracy Modeling of PWM Converters in DCM., , , , and . J. Electr. Comput. Eng., (2018)A Two-Channel Time-Interleaved Continuous-Time Third-Order CIFF-Based Delta-Sigma Modulator., , , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (12): 4729-4741 (December 2023)A 10b 700 MS/s Single-Channel 1b/Cycle SAR ADC Using a Monotonic-Specific Feedback SAR Logic With Power-Delay-Optimized Unbalanced N/P-MOS Sizing., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (12): 4767-4780 (December 2023)High-Speed and Time-Interleaved ADCs Using Additive-Neural-Network-Based Calibration for Nonlinear Amplitude and Phase Distortion., , , , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (12): 4944-4957 (2022)Bird's-eye view of analog and mixed-signal chips for the 21st century., , , , , , , , and . Int. J. Circuit Theory Appl., 49 (3): 746-761 (2021)Active-Passive ΔΣ Modulator for High-Resolution and Low-Power Applications., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (1): 364-374 (2017)