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A 16-nm SoC for Noise-Robust Speech and NLP Edge AI Inference With Bayesian Sound Source Separation and Attention-Based DNNs., , , , , , , , , и . IEEE J. Solid State Circuits, 58 (2): 569-581 (февраля 2023)Assisting High-Level Synthesis Improve SpMV Benchmark Through Dynamic Dependence Analysis., , , , и . IEEE Trans. Circuits Syst. II Express Briefs, 65-II (10): 1440-1444 (2018)A Systematic Methodology for Analysis of Deep Learning Hardware and Software Platforms., , и . MLSys, mlsys.org, (2020)Ivory: Early-Stage Design Space Exploration Tool for Integrated Voltage Regulators., , , , , , , и . DAC, стр. 1:1-1:6. ACM, (2017)DNN Engine: A 28-nm Timing-Error Tolerant Sparse Deep Neural Network Processor for IoT Applications., , , и . IEEE J. Solid State Circuits, 53 (9): 2722-2731 (2018)A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance., , , и . IEEE J. Solid State Circuits, 43 (4): 855-863 (2008)An 8×5 Gb/s Parallel Receiver With Collaborative Timing Recovery., , , и . IEEE J. Solid State Circuits, 44 (11): 3120-3130 (2009)Network Pruning for Low-Rank Binary Indexing., , , , и . CoRR, (2019)Structured Compression by Unstructured Pruning for Sparse Quantized Neural Networks., , , , , и . CoRR, (2019)Automating Design of Voltage Interpolation to Address Process Variations., , , и . IEEE Trans. Very Large Scale Integr. Syst., 19 (3): 383-396 (2011)