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RTL functional test generation using factored concolic execution., и . ITC, стр. 1-10. IEEE, (2017)Set-cover-based critical implications selection to improvesat-based bounded model checking: extended abstract., , и . ACM Great Lakes Symposium on VLSI, стр. 331-332. ACM, (2013)A novel concurrent cache-friendly binary decision diagram construction for multi-core platforms., , и . DATE, стр. 1427-1430. EDA Consortium San Jose, CA, USA / ACM DL, (2013)A new hybrid solution to boost SAT solver performance., и . DATE, стр. 1307-1313. EDA Consortium, San Jose, CA, USA, (2007)GPU-based timing-aware test generation for small delay defects., , , , , и . ETS, стр. 1-2. IEEE, (2014)A SMT-based diagnostic test generation method for combinational circuits., , , и . VTS, стр. 215-220. IEEE Computer Society, (2012)Automated Program Synthesis from Object-Oriented Natural Language for Computer Games.. CNL, том 304 из Frontiers in Artificial Intelligence and Applications, стр. 71-74. IOS Press, (2018)Sequential circuit test generation using dynamic state traversal., , и . ED&TC, стр. 22-28. IEEE Computer Society, (1997)Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation., , , , , и . VLSI Design, стр. 475-481. IEEE Computer Society, (1997)Partitioning and Reordering Techniques for Static Test Sequence Compaction of Sequential Circuits., и . Asian Test Symposium, стр. 452-457. IEEE Computer Society, (1998)