Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A 10-Gb/s 6-Vpp differential modulator driver in 65-nm CMOS., , and . ISCAS, page 1869-1872. IEEE, (2014)A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control., , and . CICC, page 1-4. IEEE, (2017)BAG2: A process-portable framework for generator-based AMS circuit design., , , , , , and . CICC, page 1-8. IEEE, (2018)4.3 An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET., , , , , , , , , and 2 other author(s). ISSCC, page 58-60. IEEE, (2021)A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET., , , , , , , , , and 21 other author(s). A-SSCC, page 285-288. IEEE, (2018)A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (9): 2691-2702 (2018)A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm., , , , , , , , and . A-SSCC, page 1-4. IEEE, (2015)A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection., , , , , , , , , and . ESSCIRC, page 384-387. IEEE, (2015)A fully integrated 1-pJ/bit 10-Gb/s/ch forwarded-clock transmitter with a resistive feedback inverter based driver in 65-nm CMOS., , and . ISCAS, page 2906. IEEE, (2016)A 6-to-32 Gb/s voltage-mode transmitter with scalable supply, voltage swing, and pre-emphasis in 65-nm CMOS., , , and . A-SSCC, page 241-244. IEEE, (2016)