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Hardware/Software Interface for Multi-Dimensional Processor Arrays.

, , and . ASAP, page 28-35. IEEE Computer Society, (2005)

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SpecHLS: Speculative Accelerator Design Using High-Level Synthesis., , and . IEEE Micro, 42 (5): 99-107 (2022)Superword level parallelism aware word length optimization., and . DATE, page 1068-1073. IEEE, (2017)Efficient hardware implementation of data-flow parallel embedded systems., , and . ICSAMOS, page 364-371. IEEE, (2012)A Reconfigurable Parallel Disk System for Filtering Genomic Banks., , , and . Engineering of Reconfigurable Systems and Algorithms, page 154-166. CSREA Press, (2003)FCCMS and the Memory Wall., and . FCCM, page 329-330. IEEE Computer Society, (2000)GeCoS: A framework for prototyping custom hardware design flows., , , , , , , , , and 3 other author(s). SCAM, page 100-105. IEEE Computer Society, (2013)Special Issue on Applied Reconfigurable Computing., and . J. Signal Process. Syst., 94 (9): 847-848 (2022)A semiempirical model for wakeup time estimation in power-gated logic clusters., , and . DAC, page 48-55. ACM, (2012)Bridging high-level synthesis and application-specific arithmetic: The case study of floating-point summations., , and . FPL, page 1-8. IEEE, (2017)Enabling Overclocking Through Algorithm-Level Error Detection., , and . FPT, page 174-181. IEEE, (2018)