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Non-Uniform Random Number Generation Through Piecewise Linear Approximations.

, and . FPL, page 1-6. IEEE, (2006)

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Hardware architectures for Monte-Carlo based financial simulations., , and . FPT, page 377-380. IEEE, (2006)A Domain Specific Language for Reconfigurable Path-based Monte Carlo Simulations., and . FPT, page 97-104. IEEE, (2007)FPGA-optimised high-quality uniform random number generators., and . FPGA, page 235-244. ACM, (2008)System-level Linking of Synthesised Hardware and Compiled Software Using a Higher-order Type System., , , and . FPGA, page 214-217. ACM, (2015)Hardware Acceleration of Matrix Multiplication over Small Prime Finite Fields., and . ARC, volume 7806 of Lecture Notes in Computer Science, page 103-114. Springer, (2013)Advancements in spiking neural network communication and synchronization techniques for event-driven neuromorphic systems., , , , and . Array, (December 2023)An Event-Driven Approach to Genotype Imputation on a Custom RISC-V Cluster., , , , , , and . IEEE ACM Trans. Comput. Biol. Bioinform., 21 (1): 26-35 (January 2024)High Quality Uniform Random Number Generation Through LUT Optimised Linear Recurrences., and . FPT, page 61-68. IEEE, (2005)Automated Framework for General-Purpose Genetic Algorithms in FPGAs., , and . EvoApplications, volume 8602 of Lecture Notes in Computer Science, page 714-725. Springer, (2014)An FPGA run-time parameterisable Log-Normal Random Number Generator., , , and . ARC, volume 4943 of Lecture Notes in Computer Science, page 219-230. Springer, (2008)